1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and more particularly, to a semiconductor device using a high dielectric constant material for a dielectric film interposed between electrodes of a capacitor.
2. Description of the Background Art
In accordance with the significant spread of information equipment such as computers, the demand for semiconductor devices is growing rapidly. Semiconductor devices having a large storage capacity and that can operate at high speed are required.
To meet these demands, technical efforts have been made to increase the integration density, response and reliability of semiconductor devices.
A DRAM (Dynamic Random Access Memory) is well known as a semiconductor device that allows random input and output of information.
A DRAM includes a memory cell array which is a memory region for storing various information, and a peripheral circuit required for carrying out input and output with an external source.
A structure of a general DRAM will be described hereinafter with reference to FIG. 76 showing a block diagram of the structure thereof.
Referring to FIG. 76, a DRAM 350 include a memory cell array 351, a row and column address buffer 352, a row decoder 353, a column decoder 354, a sense refresh amplifier 355, a data-in buffer 356, a data-out buffer 357, and a clock generator 358.
Memory cell array 351 serves to store data signals of stored information. Row and column address buffer 352 receives an externally applied address buffer signal for selecting a memory cell forming a unit memory circuit.
Row decoder 353 and column decoder 354 specify a memory cell by decoding an address buffer signal.
Sense refresh amplifier 355 amplifies and reads out a signal stored in a specified memory cell. Data-in buffer and data-out buffer 357 input or output data. Clock generator 358 generates a clock signal.
Memory cell array 351 occupies a large area on a semiconductor chip of such a DRAM. Memory cell array 351 has a plurality of memory cells arranged in a matrix for storing unit storage information.
More specifically, a memory cell includes one MOS (Metal Oxide Semiconductor) transistor, and one capacitor connected thereto.
Such a one-transistor one-capacitor type memory cell is well known. A memory cell of this structure facilitates increase of the integration density of a memory cell array due to its simple structure. Memory cells can be classified into several types according to the structure of its capacitor.
A stacked type capacitor is noteworthy for its readiness to increase the opposing area between the electrodes of a capacitor. The capacitance of a capacitor can be ensured even when the elements forming a semiconductor device are reduced in size according to the increased scale of integration. Stacked type capacitors are widely used in accordance with increase in integration density of semiconductor devices.
FIG. 77 is a sectional view of a DRAM including a conventional stacked type capacitor. Referring to FIG. 77, an isolation oxide film 333 for electrically isolating each element is formed on the surface of a silicon substrate 331.
A channel stopper region 335 is formed under isolation oxide film 333. The area of silicon substrate 331 is divided into a plurality of regions by respective isolation oxide films 333 and channel stopper regions 335. A memory cell of a DRAM is formed on the surface of an electrically isolated region of silicon substrate 331. This memory cell includes one transfer gate transistor 330 and one capacitor 320.
Transfer gate transistor 330 includes a gate oxide film 321, a gate electrode 323, and a source/drain region 325. A pair of source/drain regions 325 with a predetermined distance therebetween are formed on the surface of silicon substrate 331.
Source/drain region 325 has a LDD (Lightly Doped Drain) structure. More specifically, source/drain region 325 has a two-layered structure of an impurity region 325a of a relatively low concentration and an impurity region 325b of a relatively high concentration.
Gate electrode 323 is formed on the region sandwiched by source/drain regions 325 with gate oxide film 321 thereunder. An insulation film 327 is formed so as to cover gate electrode 323.
An insulation film 329 is formed so as to cover transfer gate transistor 330 and so as to expose partially the surface of source/drain region 325. A capacitor 320 is formed so as to come into contact with one of source/drain regions 325.
Capacitor 320 includes a lower electrode layer 313, a capacitor dielectric film 315, and an upper electrode layer 317.
Lower electrode layer (storage node) 313 is formed to come into contact with the surface of the pair of source/drain regions 325 and to extend over insulation film 329. Capacitor dielectric film 315 mainly of silicon oxide is formed to cover the surface of lower electrode layer 313.
Upper electrode layer (cell plate) 317 is formed so as to cover lower electrode layer 313 with capacitor dielectric film 315 therebetween. Charge is stored in the opposing region of lower electrode layer 313 and upper electrode layer 317 sandwiching capacitor dielectric film 315.
An interlayer insulation film 301 is formed all over the entire surface of silicon substrate 331 so as to cover capacitor 320. A contact hole 301a is formed in interlayer insulation film 301.
Contact hole 301a reaches one of the pair of source/drain regions 325. A bit line 337 is formed on interlayer insulation film 301 so as to form contact with source/drain region 325 via contact hole 301a.
Bit line 337 includes a polycrystalline silicon layer 337a and a tungsten silicide layer 337b.
More specifically, bit line 337 is formed by sequentially stacking polycrystalline silicon layer 337a and tungsten silicide layer 337b. An insulation film 319 is formed so as to cover bit line 337.
A memory cell having a stacked type capacitor as shown in FIG. 77 is suitable for increasing the integration density due to the above-described structure.
The size of a memory cell must be reduced in order to scale a DRAM to higher density. Such a reduction in the memory cell size renders the planar occupying area of a capacitor to be reduced.
As the planar occupying area is reduced, the surface area of lower electrode layer 313 is reduced substantially in proportion to the reduced rate, whereby the electrode opposing area of capacitor 320 is also reduced. This means that the amount of charge stored in the capacitor (the amount of charge stored in a memory cell of 1 bit) is reduced.
If the amount of charge stored in a memory cell of 1 bit becomes lower than a predetermined value, the operation of the DRAM as a storage region becomes unstable to degrade reliability thereof.
It is necessary to increase the capacitance of a capacitor in a limited planar occupying area in order to prevent unstable operation of a DRAM.
There are various approaches for increasing the capacitor capacitance, including:
i) reducing the thickness of the capacitor dielectric film;
ii) increasing the dielectric constant of the capacitor dielectric film.
The approach of i) has come to its limitation in the case where an interlayer insulation film is used as a capacitor dielectric film.
In order to increase the capacitance of a capacitor using a capacitor dielectric film of an interlayer insulation film, the capacitor must take a complex configuration such as a cylindrical type or bottle type capacitor.
However a capacitor with such a complex configuration requires a very difficult and tedious manufacturing process.
Recently, there has been intensive efforts in the development of increasing the dielectric constant of a capacitor, i.e. the approach of ii).
One method of increasing the dielectric constant of a capacitor dielectric film is to employ a material having a high dielectric constant such as a relative permitivity of at least 15, the so-called high dielectric constant material, as a capacitor dielectric film.
Such a high dielectric constant material has a dielectric constant several times to several hundred times that of a general interlayer insulation film. It is possible to easily increase the capacitance by using a high dielectric constant material for a capacitor dielectric film while maintaining the simple configuration of a capacitor.
Such a high dielectric constant material includes tantalum oxide (Ta.sub.2 O.sub.3), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium titanate (ST) and barium titanate (BT).
A conventional semiconductor device having a DRAM memory cell structure with a capacitor using such a high dielectric constant material as a capacitor dielectric film will be described hereinafter with reference to FIG. 78 showing a sectional view thereof.
Referring to FIG. 78, a DRAM memory cell is formed in a region isolated from other regions by an isolation oxide film 132 and a channel stopper region 133 of a silicon substrate 131.
This one transistor one-capacitor type memory cell includes a transfer gate transistor 136 and a capacitor 148.
Transfer gate transistor 136 includes a gate oxide film 137, a gate electrode 138, and a pair of source/drain regions 134/135.
On the region sandwiched by source and drain regions 134 and 135, a gate electrode 138 is formed with a gate oxide film 137 thereunder. An insulation film 139 is formed to cover the surface of gate electrode 138.
A bit line 140 is formed extending over insulation film 39 and in contact with one of source/drain regions 134/135.
An interlayer insulation film 141 is formed all over the surface of silicon substrate 131 so as to cover bit line 140 and transfer gate transistor 136.
Bit line 140 is referred to as a buried bit line since the surface thereof is covered by interlayer insulation film 141.
A contact hole 141a is formed in interlayer insulation film 141. Contact hole 141a reaches one of source/drain regions 134/135.
A buried conductive layer 142 is formed so as to fill contact hole 141a. Buried conductive layer 142 includes polycrystalline silicon having impurity implanted (referred to as "doped polysilicon" hereinafter).
The top face of buried conductive layer 142 is lower in level than the top face of interlayer insulation film 141 by a dimension r.
A capacitor 148 is formed to be electrically connected to source/drain region 135 via buried conductive layer 142.
Capacitor 148 includes a lower electrode layer 144, a high dielectric film 145, and an upper electrode layer 146. As described before, high dielectric film 145 of capacitor 148 is formed of a high dielectric constant material. Lower electrode layer 144 is formed of a platinum (Pt) layer.
Lower electrode layer 144 is formed to be electrically connected to buried conductive layer 142 via a barrier layer 143, and to extend over interlayer insulation film 141. Barrier layer 134 serves to prevent impurities in buried conductive layer 142 from diffusing into lower electrode layer 144.
A high dielectric film 145 of a high dielectric constant material is formed so as to cover the surface of lower electrode layer 144. Upper electrode layer 146 is formed so as to cover lower electrode layer 144 with high dielectric film 145 therebetween.
Upper electrode layer 146 is formed of platinum, doped polysilicon, or the like. Insulation film 147 is formed to cover the surface of capacitor 148.
A method of manufacturing the above-described semiconductor device will be described hereinafter with reference to FIGS. 79-83 schematically showing sectional views according to sequential manufacturing steps.
Referring to FIG. 79, isolation oxide film 132 is formed on the surface of silicon substrate 131 by LOCOS or the like. Simultaneously, channel stopper region 133 is formed in the region below isolation oxide film 132.
On the surface of silicon substrate 131, gate electrode 138 is formed with gate oxide film 137 thereunder. Using gate electrode 138 as a mask, ions are implanted to form source and drain regions 134 and 135.
Insulation film 139 is formed to cover gate electrode 138. Thus, transfer gate transistor 136 is formed.
Then, buried bit line 140 is formed so as to come into contact with source/drain region 134 and so as to extend over insulation film 139. Interlayer insulation film 141 is formed by CVD all over the surface of silicon substrate 131 so as to cover buried bit line 140 and transfer gate transistor 136.
Next, a photoresist of a predetermined pattern is formed all over the surface of interlayer insulation film 141. Using this photoresist pattern, etching is carried out to form contact hole 141a communicating with source/drain region 135.
Referring to FIG. 80, doped polysilicon film 142a is deposited all over the surface of interlayer insulation film 141 so as to fill the interior of contact hole 141a.
Referring to FIG. 81, doped polysilicon film 142a is etched back until the surface of interlayer insulation film 141 is exposed. An overetching of approximately 20- 30% of the film thickness of doped polysilicon film 142a is carried out to completely remove etching residues (not shown) on the surface of interlayer insulation film 141. The top face of doped polysilicon film 142a recedes from the top face of interlayer insulation film 141 by a considerable amount (dimension r) due to the so-called loading effect in addition to the overetching process.
It is to be noted that interlayer insulation film 141 is hardly etched away during this etchback process since it has a higher etching selectivity with respect to doped polysilicon film 142a. Thus, buried conductive layer 142 is formed in contact hole 141a.
Referring to FIG. 82, barrier layer 143 of Ti/TiN/Ti is formed by a sputtering method on a recess of dimension r on buried conductive layer 142. Then, a lower electrode layer 144 of platinum is layered thereon, which are patterned to a predetermined configuration.
Referring to FIG. 83, high dielectric film 145 of PZT, for example, is formed so as to cover the surface of lower electrode layer 144 by sputtering.
Then, upper electrode layer 146 of platinum, for example, is formed by a sputtering method on high dielectric film 145. Thus, capacitor 148 including lower electrode layer 144, high dielectric film 145 and upper electrode layer 146 is formed.
Then, insulation film 147 is deposited so as to cover capacitor 148 to result in the semiconductor device shown in FIG. 78.
As described above, a conventional semiconductor device is formed using a high dielectric film as a capacitor dielectric film. The potential of applying such a capacitor in a high integrated memory device, for example a DRAM of 256M, is great since the capacitance of a capacitor can be readily increased while maintaining a simple configuration of the capacitor.
The above-described conventional semiconductor device and manufacturing method thereof had problems set forth in the following.
There was the problem that the anti-leak characteristic and breakdown voltage characteristic between lower electrode layer 144 and upper electrode layer 145 forming capacitor 148 are degraded.
In the etchback process of doped polysilicon film 142a of FIGS. 80 and 81, doped polysilicon film 142a is subjected to overetching in order to completely remove etching residues on the upper surface of other portions (not shown) of interlayer insulation film 141.
When this etchback process of doped polysilicon film 142a proceeds to expose the upper surface of interlayer insulation film 141, the only exposed area of doped poiysilicon film 142a will be that remaining in contact hole 141a.
When the exposed area of a film to be etched (in this case, doped polysilicon film 142a) is rapidly reduced, the etching rate of the film to be etched will be increased by the so-called loading effect.
By a synergistic effect of an overetching process and a loading effect of doped polysilicon film 142a, the top face of buried conductive layer 142 is recessed in contact hole 141a. In other words, a recess portion (a concave) is seen in contact hole 141a.
When lower electrode layer 143 formed of platinum and capacitor dielectric film 144 formed of a high dielectric constant material are provided by a sputtering method which is poor in step coverage in this state where a recess portion exists, the portion of capacitor dielectric film 144 over the stepped portion of lower electrode layer 143 will be reduced in thickness.
FIG. 84 is a partial enlarged sectional view of the recess (P portion) shown in FIG. 78.
Referring to FIG. 84, high dielectric film 145 is reduced in thickness at the lower portion (R portion) of the recess. In the worst case, the film becomes so thin that it is terminated.
Such a reduction in film thickness of high dielectric film 145 will increase leakage current between lower electrode layer 144 and upper electrode layer 146. It is therefore difficult to ensure a predetermined breakdown voltage. In other words, satisfactory breakdown voltage and anti-leak characteristics cannot be obtained.
Furthermore, if high dielectric film 145 is not fully formed, lower electrode layer 144 will be directly in contact with upper electrode layer 146 to flaw the function of a capacitor.